Embodiments of the inventive concept relate generally to semiconductor memory devices. More particularly, embodiments of the inventive concept relate to a semiconductor memory devices in which latent power consumption is reduced.
In a read operation of a semiconductor memory device, the device receives a read command, and then outputs data after a predetermined time. The time between receipt of the read command and output of the data called column address strobe (CAS) latency (CL).
In a semiconductor memory device having multiple memory chips sharing a data transmission line, where one memory chip performs a read operation, other memory chips receive an on-die termination (ODT) command to perform a termination operation. The termination operation terminates data (i.e., prevents transmissions) to prevent data collisions on the shared transmission line.
To prevent data collisions, each memory chip performing a termination operation must terminate data with the same latency as the memory chip performing the read operation. Moreover, in a write operation, memory chips not performing the write operation must terminate data within a certain time frame. In a double data rate 3 (DDR3) semiconductor memory device, for instance, in order to increase signal fidelity, the memory chip performing the write operation is configured to terminate data at the same time as the write operation. Therefore, upon receipt of the ODT command, memory chips not performing the write operation terminate data after a delay corresponding to CAS latency.
Even a memory module having a plurality of semiconductor memory devices which share a data transmission line must terminate data in a similar manner.
In many modern semiconductor memory devices, a burst length for continuously inputting or outputting data to increase an operation speed can be designated. The burst length designates a quantity of data that can be continuously input or output in response to a single command.
In a semiconductor memory device such as a synchronous dynamic random access memory (SDRAM), a data input/output operation is performed in synchronization with a clock signal, and CAS latency is expressed as a number of cycles of the clock signal.
The semiconductor memory device operates in synchronization with the clock signal, and when a read or write command is received, data is read or written after being delayed by a number of clock cycles corresponding to the CAS latency. The data can then be read or written in a quantity corresponding to the burst length.